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8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC AD7606/AD7606-6/AD7606-4
FEATURES
8/6/4 simultaneously sampled inputs True bipolar analog input ranges: 10 V, 5 V Single 5 V analog supply and 2.3 V to 5 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 M analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 16-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPITM/MICROWIRETM/DSP compatible Performance 7 kV ESD rating on analog input channels 95.5 dB SNR, -107 dB THD 0.5 LSB INL, 0.5 LSB DNL Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package
APPLICATIONS
Power-line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS)
Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions
SingleEnded Inputs AD7608 AD7606 AD7606-6 AD7606-4 AD7607 True Differential Inputs AD7609 Number of Simultaneous Sampling Channels 8 8 6 4 8
Resolution 18 Bits 16 Bits
14 Bits
FUNCTIONAL BLOCK DIAGRAM
AVCC 1M 1M 1M 1M 1M 1M 1M 1M 1M 1M 1M 1M 1M 1M 1M 1M RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB RFB
SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF
AVCC
REGCAP
REGCAP
REFCAPB REFCAPA
V1 V1GND
CLAMP CLAMP
T/H 2.5V LDO 2.5V LDO REFIN/REFOUT T/H 2.5V REF T/H REF SELECT AGND OS 2 OS 1 OS 0 T/H SERIAL 8:1 MUX T/H 16-BIT SAR DIGITAL FILTER PARALLEL/ SERIAL INTERFACE DOUTA DOUTB RD/SCLK CS PAR/SER/BYTE SEL VDRIVE T/H PARALLEL DB[15:0]
V2 V2GND
CLAMP CLAMP
V3 V3GND
CLAMP CLAMP
V4 V4GND
CLAMP CLAMP
V5 V5GND
CLAMP CLAMP
V6 V6GND
CLAMP CLAMP
AD7606
T/H CLK OSC BUSY FRSTDATA
08479-001
V7 V7GND
CLAMP CLAMP
V8 V8GND
CLAMP CLAMP
T/H
CONTROL INPUTS
AGND
CONVST A CONVST B RESET RANGE
Figure 1.
Rev. 0
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AD7606/AD7606-6/AD7606-4 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Specifications .................................................................. 7 Absolute Maximum Ratings.......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution ................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 Typical Performance Characteristics ........................................... 17 Terminology .................................................................................... 21 Theory of Operation ...................................................................... 22 Converter Details........................................................................ 22 Analog Input ............................................................................... 22 ADC Transfer Function ............................................................. 23 Internal/External Reference ...................................................... 24 Typical Connection Diagram ................................................... 25 Power-Down Modes .................................................................. 25 Conversion Control ................................................................... 26 Digital Interface .............................................................................. 27 Parallel Interface (PAR/SER/BYTE SEL = 0).......................... 27 Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) ............... 27 Serial Interface (PAR/SER/BYTE SEL = 1) ............................. 27 Reading During Conversion ..................................................... 28 Digital Filter ................................................................................ 29 Layout Guidelines....................................................................... 32 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34
REVISION HISTORY
5/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD7606/AD7606-6/AD7606-4 GENERAL DESCRIPTION
The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous sampling, analog-to-digital data acquisition systems (DAS) with eight, six, and four channels, respectively. Each part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7606/AD7606-6/AD7606-4 operate from a single 5 V supply and can accommodate 10 V and 5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to 16.5 V. The AD7606 has 1 M analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth.
1
Patent pending. Rev. 0 | Page 3 of 36
AD7606/AD7606-6/AD7606-4 SPECIFICATIONS
VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2.
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2, 3 Test Conditions/Comments fIN = 1 kHz sine wave unless otherwise noted Oversampling by 16; 10 V range; fIN = 130 Hz Oversampling by 16; 5 V range; fIN = 130 Hz No oversampling; 10 V Range No oversampling; 5 V range No oversampling; 10 V range No oversampling; 5 V range No oversampling; 10 V range No oversampling; 5 V range Min 94 93 88.5 87.5 88 87 Typ 95.5 94.5 90 89 90 89 90.5 90 -107 -108 -110 -106 -95 23 15 10 5 11 15 16 0.5 0.5 6 12 8 8 2 7 5 16 1 3 10 5 1 6 8 8 4 8 5 16 0.99 2 Max Unit dB dB dB dB dB dB dB dB dB dB dB dB dB kHz kHz kHz kHz s s Bits LSB 4 LSB LSB LSB LSB LSB ppm/C ppm/C LSB LSB LSB LSB V/C V/C LSB LSB LSB LSB ppm/C ppm/C LSB LSB
Signal-to-(Noise + Distortion) (SINAD)2 Dynamic Range Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation2 ANALOG INPUT FILTER Full Power Bandwidth
-95
fa = 1 kHz, fb = 1.1 kHz
fIN on unselected channels up to 160 kHz -3 dB, 10 V range -3 dB, 5 V range -0.1 dB, 10 V range -0.1 dB, 5 V range 10 V Range 5 V Range No missing codes
tGROUP DELAY DC ACCURACY Resolution Differential Nonlinearity2 Integral Nonlinearity2 Total Unadjusted Error (TUE) Positive Full-Scale Error2, 5 Positive Full-Scale Error Drift Positive Full-Scale Error Matching2 Bipolar Zero Code Error2, 6 Bipolar Zero Code Error Drift Bipolar Zero Code Error Matching2 Negative Full-Scale Error2, 5 Negative Full-Scale Error Drift Negative Full-Scale Error Matching2
10 V range 5 V range External reference Internal reference External reference Internal reference 10 V range 5 V range 10 V range 5 V range 10 V range 5 V range 10 V range 5 V range External reference Internal reference External reference Internal reference 10 V range 5 V range
32
32 40 6 12
8 22 32
32 40
Rev. 0 | Page 4 of 36
AD7606/AD7606-6/AD7606-4
Parameter ANALOG INPUT Input Voltage Ranges Analog Input Current Input Capacitance 7 Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVCC VDRIVE ITOTAL Normal Mode (Static) Test Conditions/Comments RANGE = 1 RANGE = 0 10 V; see Figure 31 5 V; see Figure 31 See the Analog Input section See the ADC Transfer Function section REF SELECT = 1 REFIN/REFOUT 2.475 Min Typ Max 10 5 5.4 2.5 5 1 2.5 7.5 2.49/ 2.505 10 0.9 x VDRIVE 0.1 x VDRIVE 2 5 ISOURCE = 100 A ISINK = 100 A VDRIVE - 0.2 1 5 Twos complement All eight channels included; see Table 3 Per channel, all eight channels included 4.75 2.3 Digital inputs = 0 V or VDRIVE AD7606 AD7606-6 AD7606-4 fSAMPLE = 200 kSPS AD7606 AD7606-6 AD7606-4 16 14 12 20 18 15 5 2 4 1 200 5.25 5.25 22 20 17 27 24 21 8 6 s s kSPS V V mA mA mA mA mA mA mA A 0.2 20 2.525 1 Unit V V A A pF M V A pF V ppm/C V V A pF V V A pF
Normal Mode (Operational)8
Standby Mode Shutdown Mode
Rev. 0 | Page 5 of 36
AD7606/AD7606-6/AD7606-4
Parameter Power Dissipation Normal Mode (Static) Normal Mode (Operational) 8 Test Conditions/Comments AD7606 fSAMPLE = 200 kSPS AD7606 AD7606-6 AD7606-4 Min Typ 80 100 90 75 25 10 Max 115.5 142 126 111 42 31.5 Unit mW mW mW mW mW W
Standby Mode Shutdown Mode
1 2 3
Temperature range for the B version is -40C to +85C. See the Terminology section. This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 4 LSB means least significant bit. With 5 V input range, 1 LSB = 152.58 V. With 10 V input range, 1 LSB = 305.175 V. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode.
Rev. 0 | Page 6 of 36
AD7606/AD7606-6/AD7606-4
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3.
Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX Min Typ Max Unit Description 1/throughput rate Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 4.75 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines Serial mode reading during conversion; VDRIVE = 3.3 V Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines Conversion time Oversampling off; AD7606 Oversampling off; AD7606-6 Oversampling off; AD7606-4 Oversampling by 2; AD7606 Oversampling by 4; AD7606 Oversampling by 8; AD7606 Oversampling by 16; AD7606 Oversampling by 32; AD7606 Oversampling by 64; AD7606 STBY rising edge to CONVST x rising edge; power-up time from standby mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode RESET high pulse width BUSY to OS x pin setup time BUSY to OS x pin hold time CONVST x high to BUSY high Minimum CONVST x low pulse Minimum CONVST x high pulse BUSY falling edge to CS falling edge setup time Maximum delay allowed between CONVST A, CONVST B rising edges Maximum time between last CS rising edge and BUSY falling edge Minimum delay between RESET low to CONVST x high
5 5 9.7 tCONV 2 3.45 4 3 2 4.15
s s s s s s s s s s s s s
7.87 16.05 33 66 133 257 tWAKE-UP STANDBY tWAKE-UP SHUTDOWN Internal Reference External Reference tRESET tOS_SETUP tOS_HOLD t1 t2 t3 t4 t5 3 t6 t7 PARALLEL/BYTE READ OPERATION t8 t9 t10 50 20 20
9.1 18.8 39 78 158 315 100
30 13
ms ms ns ns ns ns ns ns ns ms ns ns
40 25 25 0 0.5 25 25
0 0 16 21 25 32 15 22
ns ns ns ns ns ns ns ns
t11 t12
CS to RD setup time CS to RD hold time RD low pulse width VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V RD high pulse width CS high pulse width (see Figure 5); CS and RD linked
Rev. 0 | Page 7 of 36
AD7606/AD7606-6/AD7606-4
Parameter t13 Limit at TMIN, TMAX Min Typ Max 16 20 25 30 t144 16 21 25 32 t15 t16 t17 SERIAL READ OPERATION fSCLK 23.5 17 14.5 11.5 t18 15 20 30 t19 4 17 23 27 34 t20 t21 t22 t23 FRSTDATA OPERATION t24 15 20 25 30 t25 15 20 25 30 t26 16 20 25 30 ns ns ns ns ns ns ns ns ns ns ns ns ns 0.4 tSCLK 0.4 tSCLK 7 22 ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz 6 6 22 ns ns ns ns ns ns ns Unit ns ns ns ns Description Delay from CS until DB[15:0] three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data access time after RD falling edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data hold time after RD falling edge CS to DB[15:0] hold time Delay from CS rising edge to DB[15:0] three-state enabled Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.7 V Data access time after SCLK rising edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V SCLK low pulse width SCLK high pulse width SCLK rising edge to DOUTA/DOUTB valid hold time CS rising edge to DOUTA/DOUTB three-state enabled Delay from CS falling edge until FRSTDATA three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS falling edge until FRSTDATA high, serial mode VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA high VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V
Rev. 0 | Page 8 of 36
AD7606/AD7606-6/AD7606-4
Parameter t27 Limit at TMIN, TMAX Min Typ Max 19 24 t28 17 22 24 ns ns ns Unit ns ns Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.7V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.7V Delay from CS rising edge until FRSTDATA three-state enabled
t29
1 2
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N x tCONV) + ((N - 1) x 1 s)). N is the oversampling ratio. For the AD7606-6, tCONV = 3 s; and for the AD7606-4, tCONV = 2 s. 3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. 4 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
t5
CONVST A, CONVST B CONVST A, CONVST B
tCYCLE t3 t1 tCONV
t2
BUSY
t4
CS RESET
t7
08479-002
tRESET
Figure 2. CONVST Timing--Reading After a Conversion
t5
CONVST A, CONVST B
tCYCLE
CONVST A, CONVST B
t2
t3 tCONV t1
BUSY
t6
CS
t7
08479-003
tRESET
RESET
Figure 3. CONVST Timing--Reading During a Conversion
CS
t8
RD
t10
t11
t9 t16 t14 t15
V4 V7 V8
t13
t17
DATA: DB[15:0]
INVALID
V1
V2
V3
FRSTDATA
t24
Figure 4. Parallel Mode, Separate CS and RD Pulses
Rev. 0 | Page 9 of 36
08479-004
t26
t27
t29
AD7606/AD7606-6/AD7606-4
t12
CS AND RD
t13
DATA: DB[15:0] V1 V2 V3 V4 V5 V6 V7
t16
V8
t17
FRSTDATA
Figure 5. CS and RD, Linked Parallel Mode
CS
SCLK
t21 t18 t19
DB15 DB14
t20 t22
DB13 DB1 DB0
08479-006
t23
DOUTA, DOUTB
t25
FRSTDATA
t28
t29
Figure 6. Serial Read Operation (Channel 1)
CS
t8 t10
RD
t9 t11 t16 t17
LOW BYTE V8
t13 t14 t15
HIGH BYTE V8 HIGH BYTE V1 LOW BYTE V1
DATA: DB[7:0]
INVALID
t26
FRSTDATA
Figure 7. BYTE Mode Read Operation
Rev. 0 | Page 10 of 36
08479-007
t24
t27
t29
08479-005
AD7606/AD7606-6/AD7606-4 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter AVCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to DGND Digital Output Voltage to GND REFIN to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range B Version Storage Temperature Range Junction Temperature Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature, Soldering Reflow ESD (All Pins Except Analog Inputs) ESD (Analog Input Pins Only)
1
THERMAL RESISTANCE
Rating -0.3 V to +7 V -0.3 V to AVCC + 0.3 V 16.5 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to AVCC + 0.3 V 10 mA -40C to +85C -65C to +150C 150C 240 (+0)C 260 (+0)C 2 kV 7 kV
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a 4-layer board. Table 5. Thermal Resistance
Package Type 64-Lead LQFP JA 45 JC 11 Unit C/W
ESD CAUTION
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 11 of 36
AD7606/AD7606-6/AD7606-4 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V8GND V7GND V6GND V5GND V4GND V3GND V2GND V1GND V8 V7 V6 V5 V4 V3 V2 V1
48 AVCC PIN 1 47 AGND 46 REFGND 45 REFCAPB 44 REFCAPA 43 REFGND 42 REFIN/REFOUT 41 AGND 40 AGND 39 REGCAP 38 AVCC 37 AVCC 36 REGCAP 35 AGND 34 REF SELECT 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
ANALOG INPUT DECOUPLING CAP PIN POWER SUPPLY GROUND PIN DATA OUTPUT DIGITAL OUTPUT DIGITAL INPUT REFERENCE INPUT/OUTPUT
AVCC 1 AGND 2 OS 0 3 OS 1 4 OS 2 5 PAR/SER/BYTE SEL 6 STBY 7 RANGE 8 CONVST A 9 CONVST B 10 RESET 11 RD/SCLK 12 CS 13 BUSY 14 FRSTDATA 15 DB0 16
AD7606
TOP VIEW (Not to Scale)
DB7/DOUTA
DB8/DOUTB
AGND
DB1
DB2
DB3
DB4
DB5
DB6
VDRIVE
DB9
DB10
DB11
DB12
DB13
DB14/HBEN
Figure 8. AD7606 Pin Configuration
V6GND
V5GND
V4GND
V3GND
V2GND
V1GND
AGND
AGND
AGND
AGND
V6
V5
V4
V3
V2
64 63 62 61 60 59 58
57 56 55 54 53 52 51 50 49 48 AVCC
ANALOG INPUT DECOUPLING CAP PIN POWER SUPPLY GROUND PIN DATA OUTPUT DIGITAL OUTPUT DIGITAL INPUT REFERENCE INPUT/OUTPUT
AVCC 1 AGND 2 OS 0 3 OS 1 4 OS 2 5 PAR/SER/BYTE SEL 6 STBY 7 RANGE 8 CONVST A 9 CONVST B 10 RESET 11 RD/SCLK 12 CS 13 BUSY 14 FRSTDATA 15 DB0 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN 1
V1
47 AGND 46 REFGND 45 REFCAPB 44 REFCAPA
AD7606-6
TOP VIEW (Not to Scale)
43 REFGND 42 REFIN/REFOUT 41 AGND 40 AGND 39 REGCAP 38 AVCC 37 AVCC 36 REGCAP 35 AGND 34 REF SELECT 33 DB15/BYTE SEL
DB7/DOUTA
DB8/DOUTB
AGND
DB1
DB2
DB3
DB4
DB5
DB6
VDRIVE
DB9
DB10
DB11
DB12
DB13
DB14/HBEN
Figure 9. AD7606-6 Pin Configuration
Rev. 0 | Page 12 of 36
08479-009
08479-008
AD7606/AD7606-6/AD7606-4
V4GND V3GND V2GND V1GND AGND AGND AGND AGND AGND AGND AGND AGND V4 V3 V2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 AVCC PIN 1 47 AGND 46 REFGND 45 REFCAPB 44 REFCAPA
ANALOG INPUT DECOUPLING CAP PIN POWER SUPPLY GROUND PIN DATA OUTPUT DIGITAL OUTPUT DIGITAL INPUT REFERENCE INPUT/OUTPUT
AVCC
1
AGND 2 OS 0 3 OS 1 4 OS 2 5 PAR/SER/BYTE SEL 6 STBY 7 RANGE 8 CONVST A 9 CONVST B 10 RESET 11 RD/SCLK 12 CS 13 BUSY 14 FRSTDATA 15 DB0 16
V1
43 REFGND 42 REFIN/REFOUT 41 AGND 40 AGND 39 REGCAP 38 AVCC 37 AVCC 36 REGCAP 35 AGND 34 REF SELECT 33 DB15/BYTE SEL
AD7606-4
TOP VIEW (Not to Scale)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DB7/DOUTA
DB8/DOUTB
AGND
DB1
DB2
DB3
DB4
DB5
DB6
VDRIVE
DB9
DB10
DB11
DB12
DB13
DB14/HBEN
Figure 10. AD7606-4 Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1, 37, 38, 48 2, 26, 35, 40, 41, 47 Type 1 P AD7606 AVCC Mnemonic AD7606-6 AVCC AD7606-4 AVCC Description Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front end amplifiers and to the ADC core. These supply pins should be decoupled to AGND. Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7606. All analog input signals and external reference signals should be referred to these pins. All six of these AGND pins should connect to the AGND plane of a system. Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for more details about the oversampling mode of operation and Table 9 for oversampling bit decoding. Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. Parallel byte interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high (see Table 8). In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA pin and the DB8/DOUTB pin function as serial data outputs. When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to ground. In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select the parallel byte mode of operation (see Table 8). DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion results in two RD operations, with DB0 as the LSB of the data transfers. Standby Mode Input. This pin is used to place the AD7606/AD7606-6/ AD7606-4 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 7. When in standby mode, all circuitry, except the onchip reference, regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down.
P
AGND
AGND
AGND
5, 4, 3
DI
OS [2:0]
OS [2:0]
OS [2:0]
6
DI
PAR/SER/ BYTE SEL
PAR/SER/ BYTE SEL
PAR/SER/ BYTE SEL
7
DI
STBY
STBY
STBY
Rev. 0 | Page 13 of 36
08479-010
AD7606/AD7606-6/AD7606-4
Pin No. 8 Type 1 DI AD7606 RANGE Mnemonic AD7606-6 RANGE AD7606-4 RANGE Description Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended for fast throughput rate applications. See the Analog Input section for more information. Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together, and a single convert start signal can be applied. Alternatively, CONVST A can be used to initiate simultaneous sampling: V1, V2, V3, and V4 for the AD7606; V1, V2, and V3 for the AD7606-6; and V1 and V2 for the AD7606-4. CONVST B can be used to initiate simultaneous sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606; V4, V5, and V6 for the AD7606-6; and V3 and V4 for the AD7606-4. This is possible only when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for the respective analog inputs is set to hold. Reset Input. When set to logic high, the rising edge of RESET resets the AD7606/AD7606-6/AD7606-4. The part should receive a RESET pulse after power-up. The RESET high pulse should typically be 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/ Serial Clock Input When the Serial Interface Is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. For more information, see the Conversion Control section. Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock out the MSB of the serial output data. Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read after a Time t4. Any data read while BUSY is high must be completed before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel, byte, or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because this clocks out the MSB of V1 on DOUTA. It returns low on the 16th SCLK falling edge after the CS falling edge. See the Conversion Control section for more details.
9, 10
DI
CONVST A, CONVST B
CONVST A, CONVST B
CONVST A, CONVST B
11
DI
RESET
RESET
RESET
12
DI
RD/SCLK
RD/SCLK
RD/SCLK
13
DI
CS
CS
CS
14
DO
BUSY
BUSY
BUSY
15
DO
FRSTDATA
FRSTDATA
FRSTDATA
Rev. 0 | Page 14 of 36
AD7606/AD7606-6/AD7606-4
Pin No. 22 to 16 Type 1 DO AD7606 DB[6:0] Mnemonic AD7606-6 DB[6:0] AD7606-4 DB[6:0] Description Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. When operating in parallel byte interface mode, DB[7:0] outputs the 16-bit conversion result in two RD operations. DB7 (Pin 24) is the MSB; DB0 is the LSB. Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP and FPGA). Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB7 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as DOUTA and outputs serial conversion data (see the Conversion Control section for more details). When operating in parallel byte mode, DB7 is the MSB of the byte. Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB8 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as DOUTB and outputs serial conversion data (see the Conversion Control section for more details). Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/ SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB14 of the conversion result. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606/ AD7606-6/AD7606-4 operate in parallel byte interface mode. In parallel byte mode, the HBEN pin is used to select whether the most significant byte (MSB) or the least significant byte (LSB) of the conversion result is output first. When HBEN = 1, the MSB is output first, followed by the LSB. When HBEN = 0, the LSB is output first, followed by the MSB. Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB15 of the conversion result. When PAR/SER/BYTE SEL = 1, the BYTE SEL pin is used to select between serial interface mode and parallel byte interface mode (see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7606 operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606 operates in parallel byte interface mode. Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be decoupled separately to AGND using a 1 F capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V. Reference Input (REFIN)/Reference Output (REFOUT). The on-chip reference of 2.5 V is available on this pin for external use if the REF SELECT pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to logic low, and an external reference of 2.5 V can be applied to this input (see the Internal/External Reference section). Decoupling is required on this pin for both the internal and external reference options. A 10 F capacitor should be applied from this pin to ground close to the REFGND pins.
23
P
VDRIVE
VDRIVE
VDRIVE
24
DO
DB7/DOUTA
DB7/DOUTA
DB7/DOUTA
25
DO
DB8/DOUTB
DB8/DOUTB
DB8/DOUTB
31 to 27
DO
DB[13:9]
DB[13:9]
DB[13:9]
32
DO/DI
DB14/ HBEN
DB14/ HBEN
DB14/ HBEN
33
DO/DI
DB15/ BYTE SEL
DB15/ BYTE SEL
DB15/ BYTE SEL
34
DI
REF SELECT
REF SELECT
REF SELECT
36, 39
P
REGCAP
REGCAP
REGCAP
42
REF
REFIN/ REFOUT
REFIN/ REFOUT
REFIN/ REFOUT
Rev. 0 | Page 15 of 36
AD7606/AD7606-6/AD7606-4
Pin No. 43, 46 44, 45 Type 1 REF REF AD7606 REFGND REFCAPA, REFCAPB V1 V1GND, V2GND V2 V3 V3GND V4 V4GND V5 V5GND V6 V6GND V7 V7GND V8 V8GND Mnemonic AD7606-6 REFGND REFCAPA, REFCAPB V1 V1GND, V2GND V2 V3 V3GND AGND AGND V4 V4GND V5 V5GND V6 V6GND AGND AGND AD7606-4 REFGND REFCAPA, REFCAPB V1 V1GND, V2GND V2 AGND AGND AGND AGND V3 V3GND V4 V4GND AGND AGND AGND AGND Description Reference Ground Pins. These pins should be connected to AGND. Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to AGND using a low ESR, 10 F ceramic capacitor. The voltage on these pins is typically 4.5 V. Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 and Analog Input Pin V2. All analog input AGND pins should connect to the AGND plane of a system. Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin Analog Input 3. For the AD7606-4, this is an AGND pin. Analog Input Ground Pin. For the AD7606-4, this is an AGND pin. Analog Input 4. For the AD7606-6 and the AD7606-4, this is an AGND pin. Analog Input Ground Pin. For the AD7606-6 and AD7606-4, this is an AGND pin. Analog Inputs. These pins are single-ended analog inputs. The analog input range of these channels is determined by the RANGE pin. Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. Analog Inputs. These pins are single-ended analog inputs. Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. Analog Input Pins. For the AD7606-4, this is an AGND pin. Analog Input Ground Pins. For the AD7606-4, this is an AGND pin. Analog Input Pin. For the AD7606-4 and AD7606-6, this is an AGND pin. Analog Input Ground Pin. For the AD7606-4 and AD7606-6, this is an AGND pin.
49 50, 52
AI AI GND
51 53 54 55 56 57 58 59 60 61 62 63 64
1
AI AI/GND AI GND/ GND AI/GND AI GND/ GND AI AI GND AI AI GND AI/GND AI GND/ GND AI/GND AI GND/ GND
P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, GND is ground.
Rev. 0 | Page 16 of 36
AD7606/AD7606-6/AD7606-4 TYPICAL PERFORMANCE CHARACTERISTICS
0 -20 -40
AMPLITUDE (dB)
-60 -80 -100 -120 -140 -160
AVCC, VDRIVE = 5V INTERNAL REFERENCE 10V RANGE FSAMPLE = 200kSPS FIN = 1kHz 16,384 POINT FFT SNR = 90.17dB THD = -106.25dB
INL (LSB)
2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 10k 20k 30k CODE
AVCC, VDRIVE = 5V FSAMPLE = 200kSPS TA = 25C INTERNAL REFERENCE 10V RANGE
08479-011
0
10k
20k
30k
40k
50k
60k
70k
80k
90k
100k
40k
50k
60k
INPUT FREQUENCY (Hz)
Figure 11. AD7606 FFT, 10 V Range
0 -20 -40
AMPLITUDE (dB)
Figure 14. AD7606 Typical INL, 10 V Range
1.0 0.8 0.6 0.4
DNL (LSB)
-60 -80 -100 -120
AVCC, VDRIVE = 5V INTERNAL REFERENCE 5V RANGE FSAMPLE = 200kSPS FIN = 1kHz 16,384 POINT FFT SNR = 89.48dB THD = -108.65dB
AVCC, VDRIVE = 5V FSAMPLE = 200kSPS TA = 25C INTERNAL REFERENCE 10V RANGE
0.2 0 -0.2 -0.4
-140 -160
08479-012
-0.6 -0.8 0 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k
08479-014 08479-015
-180 INPUT FREQUENCY (Hz)
-1.0 0 10k 20k 30k CODE 40k 50k 60k
Figure 12. AD7606 FFT Plot, 5 V Range
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 0 0.5 1.0 1.5 2.0 2.5 3.0 AVCC, VDRIVE = 5V INTERNAL REFERENCE 10V RANGE FSAMPLE = 11.5kSPS TA = 25C FIN = 133Hz 8192 POINT FFT OS BY 16 SNR = 96.01dB THD = -108.05dB 2.0 1.5 1.0 0.5
INL (LSB)
Figure 15. AD7606 Typical DNL, 10 V Range
AVCC, VDRIVE = 5V INTERNAL REFERENCE 5V RANGE FSAMPLE = 200kSPS TA = 25C
AMPLITUDE (dB)
0 -0.5 -1.0 -1.5 -2.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE
3.5
4.0
4.5
5.0
5.5
FREQUENCY (kHz)
Figure 13. FFT Plot Oversampling By 16, 10 V Range
08479-031
Figure 16. AD7606 Typical INL, 5 V Range
Rev. 0 | Page 17 of 36
08479-013
-180
AD7606/AD7606-6/AD7606-4
1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE
NFS/PFS CHANNEL MATCHING (LSB)
AVCC, VDRIVE = 5V INTERNAL REFERENCE 5V RANGE FSAMPLE = 200kSPS TA = 25C
10 8 PFS ERROR 6 4 NFS ERROR 2 0 -2 -4 -6 -9
08479-016
DNL (LSB)
-25
-10
5
20
35
50
65
80
TEMPERATURE (C)
Figure 17. AD7606 Typical DNL, 5 V Range
20 15 8 10V RANGE 5 5V RANGE 0 -5 -10 -15 -20 -40 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE
08479-017
Figure 20. NFS and PFS Error Matching
10
PFS/NFS ERROR (%FS)
10
NFS ERROR (LSB)
6
4
2
0
AVCC, VDRIVE = 5V FSAMPLE = 200 kSPS TA = 25C EXTERNAL REFERENCE SOURCE RESISTANCE IS MATCHED ON THE VxGND INPUT 10V AND 5V RANGE 0 20k 40k 60k 80k 100k 120k
08479-019 08479-023
-2 SOURCE RESISTANCE ()
-25
-10
5
20
35
50
65
80
TEMPERATURE (C)
Figure 18. NFS Error vs. Temperature
20 15 10
PFS ERROR (LSB)
Figure 21. PFS and NFS Error vs. Source Resistance
1.0 0.8
BIPOLAR ZERO CODE ERROR (LSB)
0.6 0.4 0.2 0 5V RANGE -0.2 -0.4 10V RANGE -0.6 -0.8 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -25 -10 5 20 35 50 65 80
5 0 5V RANGE -5 10V RANGE -10 -15 -20 -40 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -25 -10 5 20 35 50 65 80
08479-118
-1.0 -40
TEMPERATURE (C)
TEMPERATURE (C)
Figure 19. PFS Error vs. Temperature
Figure 22. Bipolar Zero Code Error vs. Temperature
Rev. 0 | Page 18 of 36
08479-018
-10 -40
10V RANGE AVCC, VDRIVE = 5V EXTERNAL REFERENCE
AD7606/AD7606-6/AD7606-4
BIPOLAR ZERO CODE ERROR MATCHING (LSB)
4 3 5V RANGE 2 1 10V RANGE 0 -1
SNR (dB)
98 96 94 92 90 88 86
-2 -3 -4 -40 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE
08479-024
84 82 80 10
OS BY 64 OS BY 32 OS BY 16 OS BY 8 OS BY 4 OS BY 2 NO OS 100
AVCC, VDRIVE = 5V FSAMPLE CHANGES WITH OS RATE TA = 25C INTERNAL REFERENCE 5V RANGE 1k INPUT FREQUENCY (Hz) 10k 100k
08479-020 08479-025 08479-121
-25
-10
5
20
35
50
65
80
TEMPERATURE (C)
Figure 23. Bipolar Zero Code Error Matching Between Channels
-40
Figure 26. SNR vs. Input Frequency for Different Oversampling Rates, 5 V Range
100 98 96 94
10V RANGE AVCC, VDRIVE = +5V -50 FSAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS -60 -70
THD (dB)
-80 -90 -100 -110 -120 1k 105k 48.7k 23.7k 10k 5k 1.2k 100 51 0 10k INPUT FREQUENCY (Hz) 100k
08479-021
SNR (dB)
92 90 88 86 84 82 80 10 OS BY 64 OS BY 32 OS BY 16 OS BY 8 OS BY 4 OS BY 2 NO OS 100
AVCC, VDRIVE = 5V FSAMPLE CHANGES WITH OS RATE TA = 25C INTERNAL REFERENCE 10V RANGE 1k INPUT FREQUENCY (Hz) 10k 100k
Figure 24. THD vs. Input Frequency for Various Source Impedances, 10 V Range
-40 5V RANGE AVCC, VDRIVE = +5V -50 FSAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS -60 -70
THD (dB)
Figure 27. SNR vs. Input Frequency for Different Oversampling Rates, 10 V Range
-50
CHANNEL-TO-CHANNEL ISOLATION (dB)
AVCC, VDRIVE = 5V INTERNAL REFERENCE AD7606 RECOMMENDED DECOUPLING USED FSAMPLE = 150kSPS -70 TA = 25C INTERFERER ON ALL UNSELECTED CHANNELS -80 -60 -90 10V RANGE
-80 -90 -100 -110 -120 1k 105k 48.7k 23.7k 10k 5k 1.2k 100 51 0 10k INPUT FREQUENCY (Hz) 100k
08479-122
-100 5V RANGE -110 -120 -130 -140 0 20 40 60 80 100 120 140 160 NOISE FREQUENCY (kHz)
Figure 25. THD vs. Input Frequency for Various Source Impedances, 5 V Range
Figure 28. Channel-to-Channel Isolation
Rev. 0 | Page 19 of 36
AD7606/AD7606-6/AD7606-4
100 98 96
DYNAMIC RANGE (dB)
22 10V RANGE
AVCC SUPPLY CURRENT (mA)
08479-026
20 18 16 14 12 AVCC, VDRIVE = 5V 10 TA = 25C INTERNAL REFERENCE FSAMPLE VARIES WITH OS RATE 8 NO OS OS2 OS4 OS8
94 5V RANGE 92 90 88 86 84 AVCC, VDRIVE = 5V TA = 25C 82 INTERNAL REFERENCE FSAMPLE SCALES WITH OS RATIO 80 OFF OS2 OS4 OS8
OS16
OS32
OS64
OS16
OS32
OS64
OVERSAMPLING RATIO
OVERSAMPLING RATIO
Figure 29. Dynamic Range vs. Oversampling Rate
2.5010
POWER SUPPLY REJECTION RATIO (dB)
Figure 32. Supply Current vs. Oversampling Rate
140 130 120 10V RANGE 110 5V RANGE 100 90 80 70 60 0 100 200 300 400 500 600 700 800 900 1000 1100 AVCC NOISE FREQUENCY (kHz) AVCC, VDRIVE = 5V INTERNAL REFERENCE AD7606 RECOMMENDED DECOUPLING USED FSAMPLE = 200kSPS TA = 25C
08479-030
2.5005 AVCC = 5V
REFOUT VOLTAGE (V)
AVCC = 5.25V
2.5000
2.4995 AVCC = 4.75V 2.4990
2.4985
-25
-10
5
20
35
50
65
80
TEMPERATURE (C)
Figure 30. Reference Output Voltage vs. Temperature for Different Supply Voltages
8 6 4
INPUT CURRENT (A)
08479-029
2.4980 -40
Figure 33. PSRR
AVCC, VDRIVE = 5V FSAMPLE = 200kSPS
2 0 -2 -4 -6 -8 -10 -10 +85C +25C -40C -8 -6 -4 -2 0 2 4 6 8 10
08479-028
INPUT VOLTAGE (V)
Figure 31. Analog Input Current vs. Temperature for Various Supply Voltages
Rev. 0 | Page 20 of 36
08479-027
AD7606/AD7606-6/AD7606-4 TERMINOLOGY
Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at 1/2 LSB below the first code transition; and full scale, at 1/2 LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error The deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V - 1/2 LSB. Bipolar Zero Code Error Match The absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale Error The deviation of the actual last code transition from the ideal last code transition (10 V - 11/2 LSB (9.99954) and 5 V - 11/2 LSB (4.99977)) after bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference buffer. Positive Full-Scale Error Match The absolute difference in positive full-scale error between any two input channels. Negative Full-Scale Error The deviation of the first code transition from the ideal first code transition (-10 V + 1/2 LSB (-9.99984) and -5 V + 1/2 LSB (-4.99992)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference buffer. Negative Full-Scale Error Match The absolute difference in negative full-scale error between any two input channels. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 16-bit converter, the signal-to-(noise + distortion) is 98 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7606/AD7606-6/AD7606-4, it is defined as THD (dB) = 20log
V2 2 + V3 2 + V4 2 + V5 2 + V6 2 + V 7 2 + V 8 2 + V9 2 V1
where: V1 is the rms amplitude of the fundamental. V2 to V9 are the rms amplitudes of the second through ninth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa - fb), and the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the converter's linearity. PSR is the maximum change in fullscale transition point due to a change in power supply voltage from the nominal value. The PSR ratio (PSRR) is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC's VDD and VSS supplies of Frequency fS. PSRR (dB) = 10 log (Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC output. PfS is equal to the power at Frequency fS coupled onto the AVCC supply. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 28).
Rev. 0 | Page 21 of 36
AD7606/AD7606-6/AD7606-4 THEORY OF OPERATION
CONVERTER DETAILS
The AD7606/AD7606-6/AD7606-4 are data acquisition systems that employ a high speed, low power, charge redistribution, successive approximation analog-to-digital converter (ADC) and allow the simultaneous sampling of eight/six/four analog input channels. The analog inputs on the AD7606/AD7606-6/AD7606-4 can accept true bipolar input signals. The RANGE pin is used to select either 10 V or 5 V as the input range. The AD7606/ AD7606-6/AD7606-4 operate from a single 5 V supply. The AD7606/AD7606-6/AD7606-4 contain input clamp protection, input signal scaling amplifiers, a second-order antialiasing filter, track-and-hold amplifiers, an on-chip reference, reference buffers, a high speed ADC, a digital filter, and high speed parallel and serial interfaces. Sampling on the AD7606/ AD7606-6/AD7606-4 is controlled using the CONVST signals.
Analog Input Clamp Protection
Figure 34 shows the analog input structure of the AD7606/ AD7606-6/AD7606-4. Each analog input of the AD7606/ AD7606-6/AD7606-4 contains clamp protection circuitry. Despite single 5 V supply operation, this analog input clamp protection allows for an input over voltage of up to 16.5 V.
RFB 1M Vx VxGND CLAMP 1M CLAMP RFB
08479-032
SECONDORDER LPF
Figure 34. Analog Input Circuitry
ANALOG INPUT
Analog Input Ranges
The AD7606/AD7606-6/AD7606-4 can handle true bipolar, single-ended input voltages. The logic level on the RANGE pin determines the analog input range of all analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic change on this pin has an immediate effect on the analog input range; however, there is typically a settling time of approximately 80 s, in addition to the normal acquisition time requirement. The recommended practice is to hardwire the RANGE pin according to the desired input range for the system signals.
Figure 35 shows the voltage vs. current characteristic of the clamp circuit. For input voltages of up to 16.5 V, no current flows in the clamp circuit. For input voltages that are above 16.5 V, the AD7606/AD7606-6/AD7606-4 clamp circuitry turns on.
AV , VDRIVE = 5V 30 T CC25C A=
INPUT CLAMP CURRENT (mA)
20 10 0 -10 -20 -30 -40
08479-033
Analog Input Impedance
The analog input impedance of the AD7606/AD7606-6/ AD7606-4 is 1 M. This is a fixed input impedance that does not vary with the AD7606 sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7606/AD7606-6/AD7606-4, allowing for direct connection to the source or sensor. With the need for a driver amplifier eliminated, bipolar supplies (which are often a source of noise in a system) can be removed from the signal chain.
-50 -20
-15
-10
-5
0
5
10
15
20
SOURCE VOLTAGE (V)
Figure 35. Input Protection Clamp Profile
A series resistor should be placed on the analog input channels to limit the current to 10 mA for input voltages above 16.5 V. In an application where there is a series resistance on an analog input channel, Vx, a corresponding resistance is required on the analog input GND channel, VxGND (see Figure 36). If there is no corresponding resistor on the VxGND channel, an offset error occurs on that channel.
AD7606
ANALOG INPUT SIGNAL R RC Vx VxGND 1M CLAMP 1M CLAMP RFB
08479-034
RFB
Figure 36. Input Resistance Matching on the Analog Input of the AD7606/AD7606-6/AD7606-4
Rev. 0 | Page 22 of 36
AD7606/AD7606-6/AD7606-4
Analog Input Antialiasing Filter
An analog antialiasing filter (a second-order Butterworth) is also provided on the AD7606/AD7606-6/AD7606-4. Figure 37 and Figure 38 show the frequency and phase response, respectively, of the analog antialiasing filter. In the 5 V range, the -3 dB frequency is typically 15 kHz. In the 10 V range, the -3 dB frequency is typically 23 kHz.
5 0 AV , V = 5V -5 F CC DRIVE SAMPLE = 200kSPS TA = 25C -10 -15 -20 -25 -30 -35 -40 100 10V RANGE -40 +25 +85 5V RANGE -40 +25 +85 0.1dB 10,303 9619 9326 0.1dB 5225 5225 4932 1k 3dB 24,365Hz 23,389Hz 22,607Hz 3dB 16,162Hz 15,478Hz 14,990Hz 10k 100k
08479-035
hold (that is, the delay time between the external CONVST x signal and the track-and-hold actually going into hold) is well matched, by design, across all eight track-and-holds on one device and from device to device. This matching allows more than one AD7606/AD7606-6/AD7606-4 device to be sampled simultaneously in a system. The end of the conversion process across all eight channels is indicated by the falling edge of BUSY; and it is at this point that the track-and-holds return to track mode, and the acquisition time for the next set of conversions begins. The conversion clock for the part is internally generated, and the conversion time for all channels is 4 s on the AD7606, 3 s on the AD7606-6, and 2 s on the AD7606-4. On the AD7606, the BUSY signal returns low after all eight conversions to indicate the end of the conversion process. On the falling edge of BUSY, the track-and-hold amplifiers return to track mode. New data can be read from the output register via the parallel, parallel byte, or serial interface after BUSY goes low; or, alternatively, data from the previous conversion can be read while BUSY is high. Reading data from the AD7606/AD7606-6/AD7606-4 while a conversion is in progress has little affect on performance and allows a faster throughput to be achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced by ~1.5 dB when reading during a conversion.
10V RANGE 5V RANGE
ATTENUATION (dB)
INPUT FREQUENCY (Hz)
Figure 37. Analog Antialiasing Filter Frequency Response
18 16 14 12
PHASE DELAY (s)
5V RANGE
ADC TRANSFER FUNCTION
The output coding of the AD7606/AD7606-6/AD7606-4 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is FSR/65,536 for the AD7606. The ideal transfer characteristic for the AD7606/AD7606-6/AD7606-4 is shown in Figure 39.
10V CODE = VIN x 32,768 x 10V VIN 5V CODE = x 32,768 x 5V REF 2.5V REF 2.5V
10 8 6 4 2 0 -2
10V RANGE
08479-036
10k
100k
ADC CODE
-4 AVCC, VDRIVE = 5V FSAMPLE = 200kSPS -6 TA = 25C -8 10 1k
011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000
INPUT FREQUENCY (Hz)
LSB =
+FS - (-FS) 216
Figure 38. Analog Antialias Filter Phase Response
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7606/AD7606-6/ AD7606-4 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 16-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for the track-and-
-FS + 1/2LSB 0V - 1/2LSB +FS - 3/2LSB
ANALOG INPUT
08479-037
+FS 10V RANGE +10V 5V RANGE +5V
MIDSCALE 0V 0V
-FS -10V -5V
LSB 305V 152V
Figure 39. AD7606/AD7606-6/AD7606-4 Transfer Characteristics
The LSB size is dependent on the analog input range selected.
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AD7606/AD7606-6/AD7606-4
INTERNAL/EXTERNAL REFERENCE
The AD7606/AD7606-6/AD7606-4 contain an on-chip 2.5 V bandgap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7606/AD7606-6/AD7606-4. An externally applied reference of 2.5 V is also gained up to 4.5 V, using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. The REF SELECT pin is a logic input pin that allows the user to select between the internal reference or an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7606/AD7606-6/AD7606-4 operate in the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal and external reference options. A 10 F ceramic capacitor is required on the REFIN/REFOUT pin. The AD7606/AD7606-6/AD7606-4 contain a reference buffer configured to gain the REF voltage up to ~4.5 V, as shown in Figure 40. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 F applied to REFGND, to ensure that the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. When the AD7606/AD7606-6/AD7606-4 are configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. For applications using multiple AD7606 devices, the following configurations are recommended, depending on the application requirements. External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7606 devices (see Figure 41). In this configuration, each REFIN/REFOUT pin of the AD7606/AD7606-6/AD7606-4 should be decoupled with at least a 100 nF decoupling capacitor. Internal Reference Mode One AD7606/AD7606-6/AD7606-4 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7606/AD7606-6/AD7606-4 devices, which are configured to operate in external reference mode (see Figure 42). The REFIN/ REFOUT pin of the AD7606/AD7606-6/AD7606-4, configured in internal reference mode, should be decoupled using a 10 F ceramic decoupling capacitor. The other AD7606/AD7606-6/ AD7606-4 devices, configured in external reference mode, should use at least a 100 nF decoupling capacitor on their REFIN/REFOUT pins.
REFIN/REFOUT SAR BUF REFCAPA 10F REFCAPB 2.5V REF
Figure 40. Reference Circuitry
AD7606
REF SELECT REFIN/REFOUT
AD7606
REF SELECT REFIN/REFOUT
AD7606
REF SELECT REFIN/REFOUT
100nF
100nF
08479-038
100nF
0.1F
Figure 41. Single External Reference Driving Multiple AD7606/AD7606-6/ AD7606-4 REFIN Pins
VDRIVE
AD7606
REF SELECT REFIN/REFOUT
AD7606
REF SELECT REFIN/REFOUT
AD7606
REF SELECT REFIN/REFOUT
+
Figure 42. Internal Reference Driving Multiple AD7606/AD7606-6/AD7606-4 REFIN Pins
Rev. 0 | Page 24 of 36
08479-039
10F
100nF
100nF
08479-040
ADR421
AD7606/AD7606-6/AD7606-4
TYPICAL CONNECTION DIAGRAM
Figure 43 shows the typical connection diagram for the AD7606/ AD7606-6/AD7606-4. There are four AVCC supply pins on the part, and each of the four pins should be decoupled using a 100 nF capacitor at each supply pin and a 10 F capacitor at the supply source. The AD7606/AD7606-6/AD7606-4 can operate with the internal reference or an externally applied reference. In this configuration, the AD7606 is configured to operate with the internal reference. When using a single AD7606/AD7606-6/ AD7606-4 device on the board, the REFIN/REFOUT pin should be decoupled with a 10 F capacitor. Refer to the Internal/External Reference section when using an application with multiple AD7606/AD7606-6/AD7606-4 devices. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 F ceramic capacitor. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For layout, decoupling, and grounding hints, see the Layout Guidelines section. The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7606/AD7606-6/AD7606-4 are placed in standby mode, the current consumption is 8 mA maximum and powerup time is approximately 100 s because the capacitor on the REFCAPA and REFCAPB pins must charge up. In standby mode, the on-chip reference and regulators remain powered up, and the amplifiers and ADC core are powered down. When the AD7606/AD7606-6/AD7606-4 are placed in shutdown mode, the current consumption is 6 A maximum and power-up time is approximately 13 ms (external reference mode). In shutdown mode, all circuitry is powered down. When the AD7606/ AD7606-6/AD7606-4 are powered up from shutdown mode, a RESET signal must be applied to the AD7606/AD7606-6/ AD7606-4 after the required power-up time has elapsed. Table 7. Power-Down Mode Selection
Power-Down Mode Standby Shutdown STBY 0 0 RANGE 1 0
POWER-DOWN MODES
Two power-down modes are available on the AD7606/AD7606-6/ AD7606-4: standby mode and shutdown mode. The STBY pin controls whether the AD7606/AD7606-6/AD7606-4 are in normal mode or in one of the two power-down modes.
ANALOG SUPPLY VOLTAGE 5V1 +
DIGITAL SUPPLY VOLTAGE +2.3V TO +5.25V
10F
1F
100nF
100nF
REFCAPA 10F + REFCAPB REFGND V1 V1GND V2 V2GND V3 V3GND V4 V4GND V5 V5GND V6 V6GND V7 V7GND V8 V8GND CONVST A, CONVST B CS RD BUSY AD7606 RESET OS 2 OS 1 OS 0 REF SELECT PAR/SER SEL RANGE STBY AGND DB0 TO DB15 PARALLEL INTERFACE
EIGHT ANALOG INPUTS V1 TO V8
OVERSAMPLING VDRIVE
VDRIVE
Figure 43. AD7606 Typical Connection Diagram
Rev. 0 | Page 25 of 36
08479-041
1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).
MICROPROCESSOR/ MICROCONVERTER/ DSP
REFIN/REFOUT
REGCAP2
AVCC
VDRIVE
AD7606/AD7606-6/AD7606-4
CONVERSION CONTROL
Simultaneous Sampling on All Analog Input Channels
The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST pins (CONVST A, CONVST B) are tied together. A single CONVST signal is used to control both CONVST x inputs. The rising edge of this common CONVST signal initiates simultaneous sampling on all analog input channels (V1 to V8 for the AD7606, V1 to V6 for the AD7606-6, and V1 to V4 for the AD7606-4). The AD7606 contains an on-chip oscillator that is used to perform the conversions. The conversion time for all ADC channels is tCONV. The BUSY signal indicates to the user when conversions are in progress, so when the rising edge of CONVST is applied, BUSY goes logic high and transitions low at the end of the entire conversion process. The falling edge of the BUSY signal is used to place all eight track-and-hold amplifiers back into track mode. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus (DB[15:0]), the DOUTA and DOUTB serial data lines, or the parallel byte bus, DB[7:0]. transformers. In a 50 Hz system, this allows for up to 9 of phase compensation; and in a 60 Hz system, it allows for up to 10 of phase compensation. This is accomplished by pulsing the two CONVST pins independently and is possible only if oversampling is not in use. CONVST A is used to initiate simultaneous sampling of the first set of channels (V1 to V4 for the AD7606, V1 to V3 for the AD7606-6, and V1 and V2 for the AD7606-4); and CONVST B is used to initiate simultaneous sampling on the second set of analog input channels (V5 to V8 for the AD7606, V4 to V6 for the AD7606-6, and V3 and V4 for the AD7606-4), as illustrated in Figure 44. On the rising edge of CONVST A, the track-andhold amplifiers for the first set of channels are placed into hold mode. On the rising edge of CONVST B, the track-and-hold amplifiers for the second set of channels are placed into hold mode. The conversion process begins once both rising edges of CONVST x have occurred; therefore BUSY goes high on the rising edge of the later CONVST x signal. In Table 3, Time t5 indicates the maximum allowable time between CONVST x sampling points. There is no change to the data read process when using two separate CONVST x signals. Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted.
Simultaneously Sampling Two Sets of Channels
The AD7606/AD7606-6/AD7606-4 also allow the analog input channels to be sampled simultaneously in two sets. This can be used in power-line protection and measurement systems to compensate for phase differences introduced by PT and CT
V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD CONVST A
t5
CONVST B BUSY
AD7606 CONVERTS ON ALL 8 CHANNELS
tCONV
CS/RD
DATA: DB[15:0]
V1
V2
V3
V7
V8
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FRSTDATA
Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals--Parallel Mode
Rev. 0 | Page 26 of 36
AD7606/AD7606-6/AD7606-4 DIGITAL INTERFACE
The AD7606/AD7606-6/AD7606-4 provide three interface options: a parallel interface, a high speed serial interface, and a parallel byte interface. The required interface mode is selected via the PAR/SER/BYTE SEL and DB15/BYTE SEL pins. Table 8. Interface Mode Selection
PAR/SER/BYTE SEL 0 1 1 DB15 0 0 1 Interface Mode Parallel interface mode Serial interface mode Parallel byte interface mode
When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA). When there is only one AD7606/AD7606-6/AD7606-4 in a system/board and it does not share the parallel bus, data can be read using just one control signal from the digital host. The CS and RD signals can be tied together, as shown in Figure 5. In this case, the data bus comes out of three-state on the falling edge of CS/RD. The combined CS and RD signal allows the data to be clocked out of the AD7606/AD7606-6/AD7606-4 and to be read by the digital host. In this case, CS is used to frame the data transfer of each data channel.
Operation of the interface modes is discussed in the following sections.
PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0)
Data can be read from the AD7606/AD7606-6/AD7606-4 via the parallel data bus with standard CS and RD signals. To read the data over the parallel bus, the PAR/SER/BYTE SEL pin should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low.
AD7606
BUSY 14 CS 13 RD/SCLK 12 DB[15:0] [22:16]
[33:24]
PARALLEL BYTE (PAR/SER/BYTE SEL = 1, DB15 = 1)
Parallel byte interface mode operates much like the parallel interface mode, except that each channel conversion result is read out in two 8-bit transfers. Therefore, 16 RD pulses are required to read all eight conversion results from the AD7606. For the AD7606-6, 12 RD pulses are required; and on the AD7606-4, eight RD pulses are required to read all the channel results. To configure the AD7606/AD76706-6/AD7606-4 to operate in parallel byte mode, the PAR/SER/BYTE SEL and BYTE SEL/ DB15 pins should be tied to logic high (see Table 8). In parallel byte mode, DB[7:0] are used to transfer the data to the digital host. DB0 is the LSB of the data transfer, and DB7 is the MSB of the data transfer. In parallel byte mode, DB14 acts as an HBEN pin. When DB14/HBEN is tied to logic high, the most significant byte (MSB) of the conversion result is output first, followed by the LSB of the conversion result. When DB14 is tied to logic low, the LSB of the conversion result is output first, followed by the MSB of the conversion result. The FRSTDATA pin remains high until the entire 16 bits of the conversion result from V1 are read from the AD7606/AD7606-6/AD7606-4.
INTERRUPT
Figure 45. AD7606 Interface Diagram--One AD7606 Using the Parallel Bus, with CS and RD Shorted Together
The rising edge of the CS input signal three-states the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines; it is the function that allows multiple AD7606/ AD7606-6/ AD7606-4 devices to share the same parallel data bus. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results as shown in Figure 4. A read operation of new data can take place after the BUSY signal goes low (see Figure 2); or, alternatively, a read operation of data from the previous conversion process can take place while BUSY is high (see Figure 3). The RD pin is used to read data from the output conversion results register. Applying a sequence of RD pulses to the RD pin of the AD7606/AD7606-6/AD7606-4 clocks the conversion results out from each channel onto the Parallel Bus DB[15:0] in ascending order. The first RD falling edge after BUSY goes low clocks out the conversion result from Channel V1. The next RD falling edge updates the bus with the V2 conversion result, and so on. On the AD7606, the eighth falling edge of RD clocks out the conversion result for Channel V8.
08479-043
DIGITAL HOST
SERIAL INTERFACE (PAR/SER/BYTE SEL = 1)
To read data back from the AD7606 over the serial interface, the PAR/SER/BYTE SEL pin must be tied high. The CS and SCLK signals are used to transfer data from the AD7606. The AD7606/ AD7606-6/AD7606-4 have two serial data output pins, DOUTA and DOUTB. Data can be read back from the AD7606/AD767066/AD7606-4 using one or both of these DOUT lines. For the AD7606, conversion results from Channel V1 to Channel V4 first appear on DOUTA, and conversion results from Channel V5 to Channel V8 first appear on DOUTB. For the AD7606-6, conversion results from Channel V1 to Channel V3 first appear on DOUTA, and conversion results from Channel V4 to Channel V6 first appear on DOUTB. For the AD7606-4, conversion results from Channel V1 and Channel V2 first appear on DOUTA, and conversion results from Channels V3 and Channel V4 first appear on DOUTB.
Rev. 0 | Page 27 of 36
AD7606/AD7606-6/AD7606-4
The CS falling edge takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read operation, or it can be pulsed to frame each channel read of 16 SCLK cycles. Figure 46 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7606. In this case, a 64 SCLK transfer is used to access data from the AD7606, and CS is held low to frame the entire 64 SCLK cycles. Data can also be clocked out using just one DOUT line, in which case it is recommended that DOUTA be used to access all conversion data because the channel data is output in ascending order. For the AD7606 to access all eight conversion results on one DOUT line, a total of 128 SCLK cycles is required. These 128 SCLK cycles can be framed by one CS signal, or each group of 16 SCLK cycles can be individually framed by the CS signal. The disadvantage of using just one DOUT line is that the throughput rate is reduced if reading occurs after conversion. The unused DOUT line should be left unconnected in serial mode. For the AD7606, if DOUTB is to be used as a single DOUT line, the channel results are output in the following order: V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA indicator returns low after V5 is read on DOUTB. For the AD7606-6 and the AD7606-4, if DOUTB is to be used as a single DOUT line, the channel results are output in the following order: V4, V5, V6, V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for the AD7606-4. Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7606/AD7606-6/ AD7606-4 in serial mode. The SCLK input signal provides the clock source for the serial read operation. The CS goes low to access the data from the AD7606/AD7606-6/AD7606-4. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 16-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 15 data bits are clocked out of the AD7606/ AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on the SCLK falling edge. To access each conversion result, 16 clock cycles must be provided to the AD7606/AD7606-6/AD7606-4. The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of CS takes FRSTDATA out of three-state and sets the FRSTDATA pin high, indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 16th SCLK falling edge. If all channels are read on DOUTB, the FRSTDATA output does not go high when V1 is being output on this serial data output pin. It goes high only when V1 is available on DOUTA (and this is when V5 is available on DOUTB for the AD7606).
READING DURING CONVERSION
Data can be read from the AD7606/AD7606-6/AD7606-4 while BUSY is high and the conversions are in progress. This has little effect on the performance of the converter, and it allows a faster throughput rate to be achieved. A parallel, parallel byte, or serial read can be performed during conversions and when oversampling may or may not be in use. Figure 3 shows the timing diagram for reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved when using the serial interface with VDRIVE above 4.75 V. Data can be read from the AD7606 at any time other than on the falling edge of BUSY because this is when the output data registers are updated with the new conversion data. Time t6, as outlined in Table 3, should be observed in this condition.
CS 64 SCLK
DOUTA DOUTB
V1
V2
V3
V4
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V5
V6
V7
V8
Figure 46. AD7606 Serial Interface with Two DOUT Lines
Rev. 0 | Page 28 of 36
AD7606/AD7606-6/AD7606-4
DIGITAL FILTER
The AD7606/AD7606-6/AD7606-4 contain an optional digital first-order sinc filter that should be used in applications where slower throughput rates are used or where higher signal-to-noise ratio or dynamic range is desirable. The oversampling ratio of the digital filter is controlled using the oversampling pins, OS [2:0] (see Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control bit. Table 9 provides the oversampling bit decoding to select the different oversample rates. The OS pins are latched on the falling edge of BUSY. This sets the oversampling rate for the next conversion (see Figure 48). In addition to the oversampling function, the output result is decimated to 16-bit resolution. If the OS pins are set to select an OS ratio of eight, the next CONVST x rising edge takes the first sample for each channel, and the remaining seven samples for all channels are taken with an internally generated sampling signal. These samples are then averaged to yield an improvement in SNR performance. Table 9 shows typical SNR performance for both the 10 V and the 5 V range. As Table 9 shows, there is an improvement in SNR as the OS ratio increases. As the OS ratio increases, the 3 dB frequency is reduced, and the allowed sampling frequency is also reduced. In an application where the required sampling frequency is 10 kSPS, an OS ratio of up to 16 can be used. In this case, the application sees an improvement in SNR, but the input 3 dB bandwidth is limited to ~6 kHz. The CONVST A and CONVST B pins must be tied/driven together when oversampling is turned on. When the oversampling function is turned on, the BUSY high time for the conversion process extends. The actual BUSY high time depends on the oversampling rate that is selected: the higher the oversampling rate, the longer the BUSY high, or total conversion time (see Table 3).
CONVST A AND CONVST B CONVERSION N BUSY OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 CONVERSION N + 1
CONVST A AND CONVST B
tCYCLE tCONV
19s 9s 4s BUSY
OS = 0 OS = 2 OS = 4
t4
CS
t4
t4
RD DATA: DB[15:0]
08479-046
Figure 47. AD7606--No Oversampling, Oversampling x 2, and Oversampling x 4 While Using Read After Conversion
Figure 47 shows that the conversion time extends as the oversampling rate is increased, and the BUSY signal lengthens for the different oversampling rates. For example, a sampling frequency of 10 kSPS yields a cycle time of 100 s. Figure 47 shows OS x 2 and OS x 4; for a 10 kSPS example, there is adequate cycle time to further increase the oversampling rate and yield greater improvements in SNR performance. In an application where the initial sampling or throughput rate is at 200 kSPS, for example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY high time. The falling edge of BUSY is used to update the output data registers with the new conversion data; therefore, the reading of conversion data should not occur on this edge.
tOS_HOLD
OS x
08479-045
tOS_SETUP
Figure 48. OS x Pin Timing
Table 9. Oversample Bit Decoding
OS[2:0] 000 001 010 011 100 101 110 111 OS Ratio No OS 2 4 8 16 32 64 Invalid SNR 5 V Range (dB) 89 91.2 92.6 94.2 95.5 96.4 96.9 SNR 10 V Range (dB) 90 92 93.6 95 96 96.7 97 3 dB BW 5 V Range (kHz) 15 15 13.7 10.3 6 3 1.5
Rev. 0 | Page 29 of 36
3 dB BW 10 V Range (kHz) 22 22 18.5 11.9 6 3 1.5
Maximum Throughput CONVST Frequency (kHz) 200 100 50 25 12.5 6.25 3.125
AD7606/AD7606-6/AD7606-4
Figure 49 to Figure 55 illustrate the effect of oversampling on the code spread in a dc histogram plot. As the oversample rate is increased, the spread of the codes is reduced.
1000 NO OVERSAMPLING 900 FSAMPLE = 200kSPS AVCC = 5V 800 VDRIVE = 2.5V 700 600 500 200 400 -3 131 0 -3 3 -2 -1 0 CODE (LSB) 1 2 97 2
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1400
OVERSAMPLING BY 8 FSAMPLE = 25kSPS 1200 AVCC = 5V VDRIVE = 2.5V
NUMBER OF OCCURENCES
1263
1000 800 600 400 783
928
887
NUMBER OF OCCURENCES
-2
-1
0 CODE (LSB)
1
2
3
200 100 0
Figure 52. Histogram of Codes--OS x 8 (Three Codes)
1400 3 OVERSAMPLING BY 16 FSAMPLE = 12.5kSPS 1200 AVCC = 5V VDRIVE = 2.5V
NUMBER OF OCCURENCES
1453
Figure 49. Histogram of Codes--No OS (Six Codes)
1400 OVERSAMPLING BY 2 FSAMPLE = 100kSPS 1200 AVCC = 5V VDRIVE = 2.5V
NUMBER OF OCCURENCES
1000 800 600 400 200
1148
595
1000 800 600 804
400 200 80
08479-048
-3
-2
-1
0 CODE (LSB)
1
2
3
Figure 53. Histogram of Codes--OS x 16 (Two Codes)
0 -3 0 -2 -1 0 CODE (LSB) 1 16 2 0 3
1600 OVERSAMPLING BY 32 FSAMPLE = 6.125kSPS 1400 AVCC = 5V VDRIVE = 2.5V 1417
0
Figure 50. Histogram of Codes--OS x 2 (Four Codes)
1400 OVERSAMPLING BY 4 FSAMPLE = 50kSPS 1200 AVCC = 5V VDRIVE = 2.5V
NUMBER OF OCCURENCES
NUMBER OF OCCURENCES
1200 1000 800 631 600 400 200
1262
1000 800 600 400 200 764
-3
-2
-1
0 CODE (LSB)
1
2
3
Figure 54. Histogram of Codes--OS x 32 (Two Codes)
1600
08479-049
0
0 -3
0 -2
19 -1 0 CODE (LSB) 1
3 2
0 3
OVERSAMPLING BY 64 FSAMPLE = 3kSPS 1400 AVCC = 5V VDRIVE = 2.5V
1679
NUMBER OF OCCURENCES
1200 1000 800 600 400 200 0 0 -3 0 -2 0 -1 0 CODE (LSB) 1 0 2 0 3
08479-153
Figure 51. Histogram of Codes--OS x 4 (Four Codes)
369
Figure 55. Histogram of Codes--OS x 64 (Two Codes)
Rev. 0 | Page 30 of 36
08479-152
0
0
0
0
0
0
08479-151
0
0
0
0
0
0
08479-050
300
0
0
0
2
0
0
AD7606/AD7606-6/AD7606-4
When the oversampling mode is selected for the AD7606/ AD7606-6/AD7606-4, it has the effect of adding a digital filter function after the ADC. The different oversampling rates and the CONVST sampling frequency produce different digital filter frequency profiles. Figure 56 to Figure 60 show the digital filter frequency profiles for the different oversampling rates. The combination of the analog antialiasing filter and the oversampling digital filter can be used to eliminate and reduce the complexity of the design of any filter before the AD7606/AD7606-6/AD7606-4. The digital filtering combines steep roll-off and linear phase response.
0 -10 -20
ATTENUATION (dB)
0 -10 -20
ATTENUATION (dB)
AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 16
-30 -40 -50 -60 -70 -80 -90
08479-154 08479-156 08479-155
-100 100
AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 2
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 59. Digital Filter Response for OS 16
0 -10 -20
ATTENUATION (dB)
-30 -40 -50 -60 -70 -80
08479-051
AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 32
-30 -40 -50 -60 -70 -80 -90 -100 100
-90 100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 56. Digital Filter Response for OS 2
0 -10 -20
ATTENUATION (dB)
1k
10k
100k
1M
10M
AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 4
FREQUENCY (Hz)
Figure 60. Digital Filter Response for OS 32
0 -10 AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 64
-30 -40
-20
-50 -60 -70 -80 -90
08479-052
ATTENUATION (dB)
-30 -40 -50 -60 -70 -80 -90 -100 100
-100 100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 57. Digital Filter Response for OS 4
0 -10 -20
ATTENUATION (dB)
AVCC = 5V VDRIVE = 5V TA = 25C 10V RANGE OS BY 8
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 61. Digital Filter Response for OS 64
-30 -40 -50 -60 -70 -80 -90
08479-053
-100 100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 58. Digital Filter Response for OS 8
Rev. 0 | Page 31 of 36
AD7606/AD7606-6/AD7606-4
LAYOUT GUIDELINES
The printed circuit board that houses the AD7606/AD7606-6/ AD7606-4 should be designed so that the analog and digital sections are separated and confined to different areas of the board. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7606/AD7606-6/AD7606-4. If the AD7606/AD7606-6/AD7606-4 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point that should be established as close as possible to the AD7606/AD7606-6/AD7606-4. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be allowed to run under the AD7606/AD7606-6/AD7606-4 to avoid noise coupling. Fast switching signals like CONVST A, CONVST B, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC and VDRIVE pins on the AD7606/AD7606-6/AD7606-4 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make good connections between the AD7606 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7606/AD7606-6/AD7606-4 and to reduce the magnitude of the supply spikes. The decoupling capacitors should be placed close to (ideally, right up against) these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7606/ AD7606-6/AD7606-4 pins; and, where possible, they should be placed on the same side of the board as the AD7606 device.
08479-055
08479-054
Figure 62 shows the recommended decoupling on the top layer of the AD7606 board. Figure 63 shows bottom layer decoupling, which is used for the four AVCC pins and the VDRIVE pin decoupling. Where the ceramic 100 nF caps for the AVCC pins are placed close to their respective device pins, a single 100 nF capacitor can be shared between Pin 37 and Pin 38.
Figure 62. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins
Figure 63. Bottom Layer Decoupling
Rev. 0 | Page 32 of 36
AD7606/AD7606-6/AD7606-4
To ensure good device-to-device performance matching in a system that contains multiple AD7606/AD7606-6/AD7606-4 devices, a symmetrical layout between the AD7606/AD7606-6/ AD7606-4 devices is important. Figure 64 shows a layout with two AD7606/AD7606-6/AD7606-4 devices. The AVCC supply plane runs to the right of both devices, and the VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between the two devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. These symmetrical layout principles can also be applied to a system that contains more than two AD7606/AD7606-6/AD7606-4 devices. The AD7606/AD7606-6/AD7606-4 devices can be placed in a north-south direction, with the reference voltage located midway between the devices and the reference track running in the north-south direction, similar to Figure 64.
U1 U2 AVCC
Figure 64. Layout for Multiple AD7606 Devices--Top Layer and Supply Plane Layer
Rev. 0 | Page 33 of 36
08479-056
AD7606/AD7606-6/AD7606-4 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
1 PIN 1
12.20 12.00 SQ 11.80
64 49 48
TOP VIEW
(PINS DOWN)
10.20 10.00 SQ 9.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0
16 17 32
33
0.08 COPLANARITY
VIEW A
VIEW A
ROTATED 90 CCW
0.50 BSC LEAD PITCH
0.27 0.22 0.17
051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 65. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD7606BSTZ AD7606BSTZ-RL AD7606BSTZ-6 AD7606BSTZ-6RL AD7606BSTZ-4 AD7606BSTZ-4RL EVAL-AD7606EDZ 2 EVAL-AD7606-6EDZ2 EVAL-AD7606-4EDZ2 CED1Z 3
1 2
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the AD7606 Evaluation Board for the AD7606-6 Evaluation Board for the AD7606-4 Converter Evaluation Development
Package Option ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2
Z = RoHS Compliant Part. This board can be used as a standalone evaluation board or in conjunction with the CED1Z for evaluation/demonstration purposes. 3 This board allows the PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the EDZ designator.
Rev. 0 | Page 34 of 36
AD7606/AD7606-6/AD7606-4 NOTES
Rev. 0 | Page 35 of 36
AD7606/AD7606-6/AD7606-4 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08479-0-5/10(0)
Rev. 0 | Page 36 of 36

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